Like Double Data-Rate (DDR) SDRAM, QDR SRAM transfers data on both rising and falling edges of the clock signal.
The main purpose of this capability is to enable reads and writes to occur at high clock frequencies without the loss of bandwidth due to bus-turnaround cycles incurred in DDR SRAM.
This helps to eliminate problems caused by the propagation delay of the clock wiring, and allows the illusion of concurrent reads and writes (as seen on the bus, although internally the memory still has a conventional single port - operations are pipelined but sequential).
In contrast, DDR SRAM is most efficient when only one request type is continually repeated, e.g. only read cycles.
[citation needed] QDR SRAM was designed for high-speed communications and networking applications, where data throughput is more important than cost, power efficiency or density.