The maximum random access memory (RAM) installed in any computer system is limited by hardware, software and economic factors.
Or the operating system may rely on internal data structures with fixed limits for addressable memory.
When memory devices were relatively expensive compared with the processor, often the RAM delivered with the system was much less than the address capacity of the hardware, because of cost.
Integrated circuit packages may have a limit on the number of pins available to provide the memory bus.
A trade-off might be made between address pins and other functions, restricting the memory physically available to an architecture even if it inherently has a higher capacity.
Modern 64-bit processors such as designs from ARM, Intel or AMD are typically limited to supporting fewer than 64 bits for RAM addresses.
They commonly implement from 40 to 52 physical address bits[1][2][3][4] (supporting from 1 TB to 4 PB of RAM).
Like previous architectures described here, some of these are designed to support higher limits of RAM addressing as technology improves.
This operating system was compatible with Altair 8800-like microcomputers, made by Gary Kildall in conjunction with the programming language PL/M, and was licensed to computer manufacturers by Kildall's company Digital Research after it was rejected by Intel.
An industry de facto standard was developed by the LIM consortium, composed of Lotus, Intel and Microsoft.
However the area between 640 KB and 1 MB was reserved for hardware addressing in IBM PC compatibles.
Accessing the memory above the HMA required usage of the protected mode of the 286 CPU.
Initially a de facto industry memory standard for interaction known as VCPI was developed.
These standards allowed direct access to the 16 MB space, instead of the paging scheme used by EMS and XMS.
16-bit OS/2 was limited to 15 MB, due to reserve space designed into the operating system.
Limits on memory and address space vary by platform and operating system.