The goal was to scale well, provide system-wide memory coherence and a simple interface; i.e. a standard to replace existing buses in multiprocessor systems with one with no inherent scalability and performance limitations.

[2] It was essentially a subset of Futurebus features that could be easily implemented at high speed, along with minor additions to make it easier to connect to other systems, such as VMEbus.

Representatives from companies in the computer industry and research community included Amdahl, Apple Computer, BB&N, Hewlett-Packard, CERN, Dolphin Server Technology, Cray Research, Sequent, AT&T, Digital Equipment Corporation, McDonnell Douglas, National Semiconductor, Stanford Linear Accelerator Center, Tektronix, Texas Instruments, Unisys, University of Oslo, University of Wisconsin.

This avoided the lumped capacitance, limited physical length/speed of light problems and stub reflections in addition to allowing parallel transactions.

The use of insertion rings is credited to Manolis Katevenis who suggested it at one of the early meetings of the working group.

Dolphin Interconnect Solutions implemented a PCI and PCI-Express connected derivative of SCI that provides non-coherent shared memory access.

(The other popular models for cache coherency are based on system-wide eavesdropping (snooping) of memory transactions – a scheme which is not very scalable.)

The concept of folding rings can also be applied to the Torus topologies to avoid any long connection segments.

A packet contains a header with address command and status information, payload (from 0 through optional lengths of data) and a CRC check symbol.

Modern processors with caches that are more than two orders of magnitude faster than main memory would not perform anywhere near optimal without more sophisticated methods for data consistency.

Modern systems with point-to point links use broadcast methods with snoop filter options to improve performance.

These different implementations interface to very intricate mechanisms in processors and memory systems and each vendor has to preserve some degrees of compatibility for both hardware and software.

Gustavson led a group called the Scalable Coherent Interface and Serial Express Users, Developers, and Manufacturers Association and maintained a web site for the technology starting in 1996.

After the first 1992 edition,[1] follow-on projects defined shared data formats in 1993,[5] a version using low-voltage differential signaling in 1996,[6] and a memory interface known as Ramlink later in 1996.