It is the property that "... the result of any execution is the same as if the operations of all the processors were executed in some sequential order, and the operations of each individual processor appear in this sequence in the order specified by its program.
Each processor issues memory operations in program order and the switch provides the global serialization among all memory operations[2] Sequential consistency is weaker than strict consistency.
Most instruction set architectures, including x86, x86-64, ARM, and RISC-V, do not present a sequentially consistent memory model to programs.
Some important hardware optimizations, such as write-back caching, are at odds with sequential consistency.
This means that multithreaded programs in multiprocessor systems on these architectures can exhibit behavior that is not consistent with any interleaving of the instructions on the threads, typically by reading stale values.