Source-Synchronous clocking refers to a technique used for timing symbols on a digital interface.
This type of clocking is common in high-speed interfaces between micro-chips, including DDR SDRAM, SGI XIO interface, Intel Front Side Bus for the x86 and Itanium processors, HyperTransport, SPI-4.2 and many others.
A reason that source-synchronous clocking is useful is that it has been observed that all of the circuits within a given semiconductor device experience roughly the same process-voltage-temperature (PVT) variation.
This advantage allows higher speed operation as compared to the traditional technique of providing the clock from a third device to both the transmitter and the receiver.
Another benefit is that higher complexity data-recovery or clock-data-recovery circuits (such as PLLs) are not required when this technique is used.
Synchronous logic elements such as flip-flops have static timing criteria that must be satisfied in order for them to work correctly.
The former is eliminated since both clock and data signals are driven by identical flip-flops on the same silicon at the same temperature and voltage, thereby equalizing the
This strobe clock-domain is often not synchronous to the core clock domain of the receiving device.
In bi-directional data transfer buses, two opposing unidirectional strobes can be sent from each device.