Strain engineering refers to a general strategy employed in semiconductor manufacturing to enhance device performance.
[1] The use of various strain engineering techniques has been reported by many prominent microprocessor manufacturers, including AMD, IBM, and Intel, primarily with regards to sub-130 nm technologies.
[citation needed] A second prominent approach involves the use of a silicon-rich solid solution, especially silicon-germanium, to modulate channel strain.
One manufacturing method involves epitaxial growth of silicon on top of a relaxed silicon-germanium underlayer.
Conversely, compressive strain could be induced by using a solid solution with a smaller lattice constant, such as silicon-carbon.
Another closely related method involves replacing the source and drain region of a MOSFET with silicon-germanium.
[5] Tuning this epitaxial strain can be used to moderate the properties of thin films and induce phase transitions.
After some critical film thickness, it becomes energetically favorable to relieve some mismatch strain through the formation of misfit dislocations or microtwins.
[12][13] Following this work, researchers world-wide have created such self-organized, phase-separated, nanorod/nanopillar structures in numerous oxide films as reviewed here.
[14] In 2008, Thulin and Guerra[15] published calculations of strain-modified anatase titania band structures, which included an indicated higher hole mobility with increasing strain.
[17] However, the epilayers of the LED quantum well have inherently mismatched lattice constants, creating strain between the layers.
[19] Furthermore, electro-plated metal substrates have also shown promise in applying an external counterbalancing strain to increase the overall LED efficiency.
[20] In addition to traditional strain engineering that takes place with III-N LEDs, Deep Ultraviolet (DUV) LEDs, which use AlN, AlGaN, and GaN, undergo a polarity switch from TE to TM at a critical Al composition within the active region.
[20] Furthermore, any existing lattice mismatch causes phase separation and surface roughness, in addition to creating dislocations and point defects.
The former results in local current leakage while the latter enhances the nonradiative recombination process, both reducing the device's internal quantum efficiency (IQE).
By delaying strain accumulation to grow at a thicker epilayer before reaching the target relaxation degree, certain adverse effects can be reduced.
This limits our ability to effectively modify material properties in a reversible and quantitative manner using strain.
[23] Keeping in line with Moore's law, semiconductor devices are continuously shrinking in size to the nanoscale.
Taking diamond as an example, Density Functional Theory (DFT) simulations demonstrate distinct behaviors in the bandgap decreasing rates when strained along different directions.
In the case of elastic strain, when the limit is exceeded, plastic deformation occurs due to slip and dislocation movement in the microstructure of the material.
Plastic deformation is not commonly utilized in strain engineering due to the difficulty in controlling its uniform outcome.
Plastic deformation is more influenced by local distortion rather than the global stress field observed in elastic strain.
[30] These methods of applying strain effectively enhance the electric, magnetic, thermal, and optical properties of the material.
For example, in the reference[26] provided, the optical gap of monolayer and bilayer MoS2 decreases at rates of approximately 45 and 120 meV/%, respectively, under 0-2.2% uniaxial strain.
Additionally, the photoluminescence intensity of monolayer MoS2 decreases at 1% strain, indicating an indirect-to-direct bandgap transition.