Transistor model

"Geometry" does not mean readily identified geometrical features such as a planar or wrap-around gate structure, or raised or recessed forms of source and drain (see Figure 1 for a memory device with some unusual modeling challenges related to charging the floating gate by an avalanche process).

It also refers to details inside the structure, such as the doping profiles after completion of device processing.

Although long ago the device behavior modeled in this way was very simple – mainly drift plus diffusion in simple geometries – today many more processes must be modeled at a microscopic level; for example, leakage currents[1] in junctions and oxides, complex transport of carriers including velocity saturation and ballistic transport, quantum mechanical effects, use of multiple materials (for example, Si-SiGe devices, and stacks of different dielectrics) and even the statistical effects due to the probabilistic nature of ion placement and carrier transport inside the device.

The models may require change to reflect new physical effects, or to provide greater accuracy.

These models are very computer intensive, involving detailed spatial and temporal solutions of coupled partial differential equations on three-dimensional grids inside the device.

[7] Nonlinear, or large signal transistor models fall into three main types:[8][9] Small-signal or linear models are used to evaluate stability, gain, noise and bandwidth, both in the conceptual stages of circuit design (to decide between alternative design ideas before computer simulation is warranted) and using computers.

As long as the signal is small relative to the nonlinearity of the device, the derivatives do not vary significantly, and can be treated as standard linear circuit elements.