Universal asynchronous receiver-transmitter
Some early telegraph schemes used variable-length pulses (as in Morse code) and rotating clockwork mechanisms to transmit alphabetic characters.
Gordon Bell of DEC designed the first UART, occupying an entire circuit board called a line unit, for the PDP series of computers beginning with the PDP-1.
An example of an early 1980s UART was the National Semiconductor 8250, which was used in the original IBM PC's Asynchronous Communications Adapter card.
Intel called their 8251 device a "Programmable Communication Interface" because it was actually a USART and capable of synchronous operation as well as asynchronous.
In most applications, the least significant data bit (the one on the left in this diagram) is transmitted first, but there are exceptions (such as the IBM 2741 printing terminal).
After waiting a further bit time, the state of the line is again sampled and the resulting level clocked into a shift register.
Typically, UARTs resynchronize their internal clocks on each change of the data line that is not considered a spurious pulse.
Many UARTs have a small first-in, first-out (FIFO) buffer memory between the receiver shift register and the host system interface.
This allows the host processor even more time to handle an interrupt from the UART and prevents loss of received data at high rates.
The receiving UART may detect some mismatched settings and set a "framing error" flag bit for the host system; in exceptional cases, the receiving UART will produce an erratic stream of mutilated characters and transfer them to the host system.
The 28L91 is an upwardly compatible version of the 2691, featuring selectable 8- or 16-byte transmitter and receiver FIFOs, improved support for extended data rates, and faster bus timing characteristics, making the device more suitable for use with high performance microprocessors.
The devices are produced in PDIP-40, PLCC-44 and 44 pin QFP packages, and are readily adaptable to both Motorola and Intel buses.
The 26C92 is an upwardly compatible version of the 2692, with 8-byte transmitter and receiver FIFOs for improved performance during continuous bi-directional asynchronous transmission (CBAT) on both channels at the maximum standard speed of 230.4 kbit/s.
The 28L92 is an upwardly compatible version of the 26C92, featuring selectable 8- or 16-byte transmitter and receiver FIFOs, improved support for extended data rates, and faster bus timing characteristics, making the device more suitable for use with high performance microprocessors.
The devices are produced in PDIP-40, PLCC-44 and 44 pin QFP packages, and are readily adaptable to both Motorola and Intel buses.
Modems for personal computers that plug into a motherboard slot must also include the UART function on the card.
The original 8250 UART chip shipped with the IBM personal computer had a one-character buffer for the receiver and the transmitter each, which meant that communications software performed poorly at speeds above 9600 bit/s, especially if operating under a multitasking system or if handling interrupts from disk controllers.
[citation needed][dubious – discuss] Some hard disk drives and video controllers violate this specification.
9600 bit/s will deliver a character approximately every millisecond, so a 1-byte FIFO should be sufficient at this rate on a DOS system which meets the maximum interrupt disable timing.
This increases the maximum bit rate the computer can process reliably from 9600 to 153,000 bit/s if it has a 1 millisecond interrupt dead time.
A second benefit to having a FIFO is that the computer only has to service about 8 to 12% as many interrupts, allowing more CPU time for updating the screen, or doing other chores.
Since the UART's communication protocol is simple, it can be emulated by bit banging GPIO pins in software on modern microcontrollers (e.g. Arduino[18] or Teensy[19]), or on programmable I/O state machines (e.g. Raspberry Pi Pico's PIO[20][21] or NXP's FlexIO[22]).
