The WDC 65C816 adds a fourth hardware interrupt—ABORT, useful for implementing virtual memory architectures—and the COP software interrupt instruction (also present in the 65C802), intended for use in a system with a coprocessor of some type (e.g., a floating-point processor).
[1][2] The hardware interrupt signals are all active low, and are as follows:[1] The detection of a RESET signal causes the processor to enter a system initialization period of six clock cycles, after which it sets the interrupt request disable flag in the status register and loads the program counter with the values stored at the processor initialization vector ($00FFFC–$00FFFD) before commencing execution.
The detection of an NMI or IRQ signal, as well as the execution of a BRK instruction, will cause the same overall sequence of events, which are, in order:[1][3] The behavior of the 65C816 when ABORT is asserted differs in some respects from the above description and is separately discussed below.
[2] The 65C816's ABORTB interrupt input is intended to provide the means to redirect program execution when a hardware exception is detected, such as a page fault or a memory access violation.
In order for the processor to correctly respond to an abort, system logic must assert (negate) the ABORTB input as soon as a valid address has been placed on the bus and it has been determined that the address constitutes a page fault, memory access violation or other anomaly (e.g., attempted execution of a privileged instruction).
[2] In most ISRs, the accumulator and/or index registers must be preserved to assure transparency and later restored as the final steps prior to executing RTI.
[5] Therefore, the following ISR entry code is typical: The CLD instruction is necessary because, as previously noted, NMOS versions of the 6502 do not clear the D (decimal mode) flag in the status register when an interrupt occurs.
Again, the following NMOS code is typical: A consequence of the RTI instruction is the MPU will return to decimal mode if that was its state at the time of the interrupt.
[2] Pushing the accumulator when it is set to 8 bits will not preserve .B,[2] which could result in a loss of transparency should the ISR change .B in any way.
As previously noted, BRK and COP are software interrupts and, as such, may be used in a variety of ways to implement system functions.
A typical technique in firmware development was to arrange for the BRK vector to point to an unprogrammed "patch area" in the PROM.
If BRK is used as a debugging device, the program counter may have to be adjusted to point to the signature in order for execution to resume where expected.
The fact that BRK and COP double-increment the program counter before pushing it to the stack facilitates the technique of treating them as supervisor call instructions, as found on some mainframe computers.
The operating system BRK or COP handler would retrieve the value of the program counter pushed to the stack, decrement it and read from the resulting memory location to get the signature.
[8][9] After converting the signature to a zero-based index, a simple lookup table can be consulted to load the program counter with the address of the proper service routine.
Upon completion of the service routine, the RTI instruction would be used to return control to the program that made the operating system call.
Also, as executing BRK or COP always vectors the processor to the same address, simple code may be used to preserve the registers on the stack prior to turning control over to the requested service.
Upon receipt of an IRQ, the MPU will "awaken" in one clock cycle and resume execution at the instruction immediately following WAI.
Similar in some ways to WAI is the STP (SToP, opcode $DB) instruction, which completely shuts down the MPU while waiting for a single interrupt input.
[2] When STP is executed, the MPU halts its internal clock in the high phase, retaining all data in its registers, and enters a low power state.