Chip-scale package

[1] Originally, CSP was the acronym for chip-size packaging.

According to IPC's standard J-STD-012, Implementation of Flip Chip and Chip Scale Technology, in order to qualify as chip scale, the package must have an area no greater than 1.2 times that of the die and it must be a single-die, direct surface mountable package.

Another criterion that is often applied to qualify these packages as CSPs is their ball pitch should be no more than 1 mm.

The concept was first proposed by Junichi Kasai of Fujitsu and Gen Murakami of Hitachi Cable in 1993.

WL-CSP had been in development since 1990s, and several companies begun volume production in early 2000, such as Advanced Semiconductor Engineering (ASE).