According to the 2007 edition of the roadmap, by the year 2022, the half-pitch (i.e., half the distance between identical features in an array) for a DRAM was projected to be 11 nm.
[8][needs update] In 2012, Samsung announced eMMC flash memory chips that are produced using the "10 nm" process.
[11] On 17 October 2016, Samsung Electronics announced mass production of SoC chips at "10 nm".
[12] The technology's main announced challenge at that time had been triple patterning for its metal layer.
[15] On 21 April 2017, Samsung started shipping their Galaxy S8 smartphone, which used the company's version of the "10 nm" processor.
In April 2018, Intel announced a delay in volume production of "10 nm" mainstream CPUs until sometime in 2019.
In addition, the transistor fin height of Samsung's "10 nm" process was updated by MSSCORPS CO at SEMICON Taiwan 2017.
[41][needs update] For the DRAM industry, the term "10 nm-class" is often used and this dimension generally refers to the half-pitch of the active area.
[45] Beyond 1z Samsung named its next node (fourth generation "10 nm class") DRAM : "D1a" (expected at that time to have been produced in 2021), and beyond that "D1b" (expected at that time to have been produced in 2022)[needs update]; whilst Micron referred[needs update] to succeeding "nodes" as "D1α" and "D1β".