The 65 nm process is an advanced lithographic node used in volume CMOS (MOSFET) semiconductor fabrication.
A crystal of bulk silicon has a lattice constant of 0.543 nm, so such transistors are on the order of 100 atoms across.
By September 2007, Intel, AMD, IBM, UMC and Chartered were also producing 65 nm chips.
Fabrication of sub-wavelength features requires special imaging technologies, such as optical proximity correction and phase-shifting masks.
The new chemistry of high-κ gate dielectrics must be combined with existing techniques, including substrate bias and multiple threshold voltages, to prevent leakage from prohibitively consuming power.