[2] The primary advantage of AGP is that it doesn't share the PCI bus, providing a dedicated, point-to-point pathway between the expansion slot(s) and the motherboard chipset.

The card may send many address phases, so the host can process them in order, avoiding any long delays caused by the bus being idle during read operations.

Intel introduced AGP support with the i440LX Slot 1 chipset on August 26, 1997, and a flood of products followed from all the major system board vendors.

[5] Early video chipsets featuring AGP support included the Rendition Vérité V2200, 3dfx Voodoo Banshee, Nvidia RIVA 128, 3Dlabs PERMEDIA 2, Intel i740, ATI Rage series, Matrox Millennium II, and S3 ViRGE GX/2.

Microsoft first introduced AGP support into Windows 95 OEM Service Release 2 (OSR2 version 1111 or 950B) via the USB SUPPLEMENT to OSR2 patch.

Linux support for AGP enhanced fast data transfers was first added in 1999 with the implementation of the AGPgart kernel module.

As GPUs began to be designed to connect to PCIe, an additional PCIe-to-AGP bridge-chip was required to create an AGP-compatible graphics card.

The inclusion of a bridge, and the need for a separate AGP card design, incurred additional board costs.

In 2011 DirectX 10-capable AGP cards from AMD vendors (Club 3D, HIS, Sapphire, Jaton, Visiontek, Diamond, etc.)

Possible future removal of support for AGP from open-source Linux kernel drivers was considered in 2020.

Upgraded registers include PCISTS, CAPPTR, NCAPID, AGPSTAT, AGPCMD, NISTAT, NICMD.

New required registers include APBASELO, APBASEHI, AGPCTRL, APSIZE, NEPG, GARTLO, GARTHI.

An official extension for cards that required more electrical power, with a longer slot with additional pins for that purpose.

An important part of initialization is telling the card the maximum number of outstanding AGP requests which may be queued at a given time.

Whenever the PCI GNT# signal is asserted, granting the bus to the card, three additional status bits ST[2:0] indicate the type of transfer to be performed next.

For every cycle that PIPE# is asserted, the card sends another request without waiting for acknowledgement from the motherboard, up to the configured maximum queue depth.

The possible values are: Sideband address bytes are sent at the same rate as data transfers, up to 8× the 66 MHz basic bus clock.

Sideband addressing has the advantage that it mostly eliminates the need for turnaround cycles on the AD bus between transfers, in the usual case when read operations greatly outnumber writes.

While asserting GNT#, the motherboard may instead indicate via the ST bits that a data phase for a queued request will be performed next.

For each cycle when the GNT# is asserted and the status bits have the value 00p, a read response of the indicated priority is scheduled to be returned.

At the next available opportunity (typically the next clock cycle), the motherboard will assert TRDY# (target ready) and begin transferring the response to the oldest request in the indicated read queue.

If the response is longer than that, both the card and motherboard must indicate their ability to continue on the third cycle by asserting IRDY# (initiator ready) and TRDY#, respectively.

For each cycle when GNT# is asserted and the status bits have the value 01p, write data is scheduled to be sent across the bus.

At the next available opportunity (typically the next clock cycle), the card will assert IRDY# (initiator ready) and begin transferring the data portion of the oldest request in the indicated write queue.

The multiplier in AGP 2×, 4× and 8× indicates the number of data transfers across the bus during each 66 MHz clock cycle.

In such a case, the cycle is padded with dummy data transfers (with the C/BE# byte enable lines held deasserted).