Bus (computing)

[3] At its core, a bus is a shared physical pathway, typically composed of wires, traces on a circuit board, or busbars, that allows multiple devices to communicate.

Modern buses utilize both parallel and serial communication, employing advanced encoding methods to maximize speed and efficiency.

As the buses became wider and lengthier, this approach became expensive in terms of the number of chip pins and board traces.

Accessing an individual byte frequently requires reading or writing the full bus width (a word) at once.

In these instances the least significant bits of the address bus may not even be implemented - it is instead the responsibility of the controlling device to isolate the individual byte required from the complete word transmitted.

As data rates increase, the problems of timing skew, power consumption, electromagnetic interference and crosstalk across parallel buses become more and more difficult to circumvent.

[4] Network connections such as Ethernet are not generally regarded as buses, although the difference is largely conceptual rather than practical.

This excludes, as buses, schemes such as serial RS-232, parallel Centronics, IEEE 1284 interfaces and Ethernet, since these devices also needed separate power supplies.

Such avionic data buses are usually characterized by having several equipments or Line Replaceable Items/Units (LRI/LRUs) connected to a common, shared media.

To reduce cost, most microcomputers have a bidirectional data bus, re-using the same wires for input and output at different times.

Bus multiplexing requires fewer wires, which reduces costs in many early microprocessors and DRAM chips.

Over time, several groups of people worked on various computer bus standards, including the IEEE Bus Architecture Standards Committee (BASC), the IEEE Superbus study group, the open microprocessor initiative (OMI), the open microsystems initiative (OMI), the Gang of Nine that developed EISA, etc.

Anecdotally termed the digit trunk in the early Australian CSIRAC computer,[21] they were named after electrical power buses, or busbars.

High-end systems introduced the idea of channel controllers, which were essentially small computers dedicated to handling the input and output of a given bus.

Generally, the channel controllers would do their best to run all of the bus operations internally, moving data when the CPU was known to be busy elsewhere if possible, and only using interrupts when necessary.

In this case signals will naturally flow through the bus in physical or logical order, eliminating the need for complex scheduling.

[23] Early microcomputer bus systems were essentially a passive backplane connected directly or through buffer amplifiers to the pins of the CPU.

Memory and other devices would be added to the bus using the same address and data pins as the CPU itself used, connected in parallel.

In some instances, most notably in the IBM PC, although similar physical architecture can be employed, instructions to access peripherals (in and out) and memory (mov and others) have not been made uniform at all, and still generate distinct CPU signals, that could be used to implement a separate I/O bus.

They typically separated the computer into two address spaces, the CPU and memory on one side, and the various peripheral devices on the other.

The result was that the bus speeds were now much slower than what a modern system needed, and the machines were left starved for data.

By 2004 AGP was outgrown again by high-end video cards and other peripherals and has been replaced by the new PCI Express bus.

This can lead to complex problems when trying to service different requests, so much of the work on these systems concerns software design, as opposed to the hardware itself.

Buses such as Wishbone have been developed by the open source hardware movement in an attempt to further remove legal and patent constraints from computer design.

The Compute Express Link (CXL) is an open standard interconnect for high-speed CPU-to-device and CPU-to-memory, designed to accelerate next-generation data center performance.