Every step in the IC design (such as static timing analysis, placement, routing, and so on) is already complex and often forms its own field of study.
In the early days of VLSI, a chip consisted of a few thousand logic circuits that performed a simple function at speeds of a few MHz.
The complexity of the flow is a direct result of the addition and evolution of the list of design closure constraints.
In the mid-1990s (180 nm node), industry visionaries were describing the impending dangers of coupling noise long before chips were failing.
Constraints tend to move up in the flow due to one of the basic paradoxes of design: accuracy vs. influence.
For example, an architectural decision to pipeline a logic function can have a far greater impact on total chip performance than any amount of postrouting fix-up.
At the same time, accurately predicting the performance impact of such a change before the chip logic is synthesized, let alone placed or routed, is very difficult.
In the past if there were too many timing constraint violations left after routing, it was necessary to loop back, modify the tool settings slightly, and reexecute the previous placement steps.
If the constraints were still not met, it was necessary to reach further back in the flow and modify the chip logic and repeat the synthesis and placement steps.