Moore's law has driven the entire IC implementation RTL to GDSII design flows[clarification needed] from one which uses primarily stand-alone synthesis, placement, and routing algorithms to an integrated construction and analysis flows for design closure.
The challenges of rising interconnect delay led to a new way of thinking about and integrating design closure tools.
The continued scaling of CMOS technologies significantly changed the objectives of the various design steps.
The lack of good predictors for delay has led to significant changes in recent design flows.
New scaling challenges such as leakage power, variability, and reliability will continue to require significant changes to the design closure process in the future.