Dual-ported video RAM

This makes it easy to interface with a Video display controller (VDC), which sends a timing signal to the memory and receives data in the correct sequence as it draws the screen.

It also almost always communicated over a slow System bus that limited the speed that changes to the screen could be made, making interactive graphics difficult.

Prior to the development of VRAM, dual-ported memory was quite expensive, limiting higher resolution bitmapped graphics to high-end workstations.

Modern GUI-based operating systems benefitted from this and thus it provided a key ingredient for proliferation of Graphical user interfaces (GUI's) throughout the world at that time.

Dynamic RAM is internally arranged in an array of rows and columns of capacitors, with each row/column intersection holding a single bit in a cell.

VRAM generally does not have two address buses, meaning that the CPU and graphics still have to interleave their accesses to the chip, but as a whole row of data is read out to the graphics driver, and that row might represent multiple scan lines on the screen, the number of times it has to interrupt the CPU can be greatly reduced.

[2] Such operation is described in the paper "All points addressable raster display memory" by R. Matick, D. Ling, S. Gupta, and F. Dill, IBM Journal of R&D, Vol 28, No.

Each SCLK pulse causes the VRAM to deliver the next data [computing] in strict address order, from the shift register to the video port.

In the late 1990s, SDRAM technologies gradually became affordable, dense, and fast enough to displace VRAM, even though it is only single-ported and more overhead is required.