Emitter-coupled logic

ECL uses an overdriven bipolar junction transistor (BJT) differential amplifier with single-ended input and limited emitter current to avoid the saturated (fully on) region of operation and the resulting slow turn-off behavior.

As a result, the transistors change states quickly, gate delays are low, and the fanout capability is high.

[6] In addition, the essentially constant current draw of the differential amplifiers minimizes delays and glitches due to supply-line inductance and capacitance, and the complementary outputs decrease the propagation time of the whole circuit by reducing inverter count.

ECL's major disadvantage is that each gate continuously draws current, which means that it requires (and dissipates) significantly more power than those of other logic families, especially when quiescent.

"The disadvantages are that more different power supply voltages are needed, and both pnp and npn transistors are required.

[17] Beginning in the early 1960s, ECL circuits were implemented on monolithic integrated circuits and consisted of a differential-amplifier input stage to perform logic and followed by an emitter-follower stage to drive outputs and shift the output voltages so they will be compatible with the inputs.

By 1991, the CMOS NVAX was launched which offered comparable performance to the VAX 9000 despite costing 25 times less and consuming considerably less power.

The left half of the pair (shaded yellow) consists of two parallel-connected input transistors T1 and T2 (an exemplary two-input gate is considered) implementing NOR logic.

During the transition, the core of the circuit – the emitter-coupled pair (T1 and T3) – acts as a differential amplifier with single-ended input.

The input voltage controls the current flowing through the transistors by sharing it between the two legs, steering it all to one side when not near the switching point.

The circuit is insensitive to the input voltage variations and the transistor stays firmly in active linear region.

Other noteworthy characteristics of the ECL family include the fact that the large current requirement is approximately constant, and does not depend significantly on the state of the circuit.

This means that ECL circuits generate relatively little power noise, unlike other logic types which draw more current when switching than quiescent.

In cryptographic applications, ECL circuits are also less susceptible to side channel attacks such as differential power analysis.

[citation needed] The propagation time for this arrangement can be less than a nanosecond, including the signal delay getting on and off the IC package.

If the negative end of the power supply was grounded, the collector resistors would be attached to the positive rail.

The fact that the high and low logic levels are relatively close meant that ECL suffers from small noise margins, which can be troublesome.

Motorola ECL 10,000 basic gate circuit diagram from 1972. [ 1 ] Note the Q5 and Q6 emitters coupled to the output.
Yourke's current switch (around 1955) [ 9 ]
The picture represents a typical ECL circuit diagram based on Motorola's MECL. In this schematic, transistor T5′ represents the output transistor of a previous ECL gate that provides a logic signal to input transistor T1 of an OR/NOR gate whose other input is at T2 and has outputs Y and Y . Additional pictures illustrate the circuit operation by visualizing the voltage relief and current topology at low input voltage (logical "0"), during the transition and at high input voltage (logical "1").