This original chip was manufactured using 1.2 μm CMOS technology and operates in the 20 kHz range at a power consumption of 80 mW.
The reconfigurable analog signal processor (RASP) and a second version were introduced in 2002 by Hall et al.[6][7] Their design incorporated high-level elements such as second order bandpass filters and 4 by 4 vector matrix multipliers into the CABs.
In 2004 Joachim Becker picked up the parallel connection of OTAs (operational transconductance amplifiers) and proposed its use in a hexagonal local interconnection architecture.
In 2005 Fabian Henrici worked with Joachim Becker to develop a switchable and invertible OTA which doubled the maximum FPAA bandwidth.
In 2016 Dr. Jennifer Hasler from Georgia Tech designed a FPAA system on a chip that uses analog technology to achieve unprecedented power and size reductions.