SuperH
However for the market the SuperH was aimed at, this was a small price to pay for the improved memory and processor cache efficiency.
In 2015, many of the original patents for the SuperH architecture expired and the SH-2 CPU was reimplemented as open source hardware under the name J2.
The design concept was for a single instruction set (ISA) that would be upward compatible across a series of CPU cores.
One of the key realizations during the development of the RISC concept was that the microcode had a finite decoding time, and as processors became faster, this represented an unacceptable performance overhead.
To address this, Hitachi instead developed a single ISA for the entire line, with unsupported instructions causing traps on those implementations that didn't include hardware support.
The SH-2 added 64-bit multiplication and a few additional commands for branching and other duties, bringing the total to 62 supported instructions.
In 2004, Renesas Technology bought STMicroelectronics's share of ownership in the SuperH Inc. and with it the licence to the SH cores.
The combination of a compact 16-bit instruction encoding with a more powerful 32-bit instruction encoding is not unique to SH-5; ARM processors have a 16-bit Thumb mode (ARM licensed several patents from SuperH for Thumb[11]) and MIPS processors have a MIPS-16 mode.
The system-on-chip products based on SH-3, SH-4 and SH-4A microprocessors were subsequently replaced by newer generations based on licensed CPU cores from Arm Ltd., with many of the existing models still marketed and sold until March 2025 through the Renesas Product Longevity Program.
At LinuxCon Japan 2015, j-core developers presented a cleanroom reimplemention of the SH-2 ISA with extensions (known as the "J2 core" due to the unexpired trademarks).
[14] The open source BSD-licensed VHDL code for the J2 core has been proven on Xilinx FPGAs and on ASICs manufactured on TSMC's 180 nm process, and is capable of booting μClinux.
[11][needs update] Several features of SuperH have been cited as motivations for designing new cores based on this architecture:[11] The family of SuperH CPU cores includes: The SH-2 is a 32-bit RISC architecture with a 16-bit fixed instruction length for high code density and features a hardware multiply–accumulate (MAC) block for DSP algorithms and has a five-stage pipeline.
The SH-4 is a RISC CPU and was developed for primary use in multimedia applications, such as Sega's Dreamcast and NAOMI game systems.
It includes a much more powerful floating-point unit[note] and additional built-in functions, along with the standard 32-bit integer processing and 16-bit instruction size.
[18] Almost no non-simulated SH-5 hardware was ever released,[19] and, unlike the still-live SH-4, support for SH-5 was dropped from GCC[20] and Linux.
