It relies on measuring the supply current (Idd) in the quiescent state (when the circuit is not switching and inputs are held at static values).
Iddq testing uses the principle that in a correctly operating quiescent CMOS digital circuit, there is no static current path between the power supply and ground, except for a small amount of leakage.
Many common semiconductor manufacturing faults will cause the current to increase by orders of magnitude, which can be easily detected.
If a line is shorted to Vdd, for example, it will still draw no extra current if the gate driving the signal is attempting to set it to '1'.
As device geometry shrinks, i.e transistors and gates become smaller resulting in larger and more complex processors and SoCs (see Moore's law), the leakage current becomes much higher and less predictable.
Also, increasing circuit size means a single fault will have a lower percentage effect, making it harder for the test to detect.