Typically, high threshold voltage (Vth) sleep transistors are used for power gating in a technique sometimes known as multi-threshold CMOS (MTCMOS).
[1][2] Adding a sleep transistor to every cell that is to be turned off imposes a large area penalty, and individually gating the power of every cluster of cells creates timing issues introduced by inter-cluster voltage variation that are difficult to resolve.
Fine-grain power gating encapsulates the switching transistor as a part of the standard cell logic.
The size of the gate control is designed considering the worst-case scenario that will require the circuit to switch during every clock cycle, resulting in a huge area impact.
Some of the recent designs implement the fine-grain power gating selectively, but only for the low Vth cells.
Otherwise it can cause the neighboring high Vth cell to have leakage when output goes to an unknown state due to power gating.
The inherent difference between when a cell switches off with respect to another, minimizes the rush current during switch-on and switch-off.
Fine-grain power gating is an elegant methodology resulting in up to 10 times leakage reduction.
The coarse-grained approach implements the grid style sleep transistors which drives cells locally through shared virtual power networks.
There are two ways of implementing a coarse-grain structure: Gate sizing depends on the overall switching current of the module at any given time.
Simultaneous switching capacitance is a major consideration in coarse-grain power gating implementation.
Isolation cells are specially designed for low short circuit current when input is at threshold voltage level.
For critical applications, the memory states must be maintained within the cell, a condition that requires a retention flop to store bits in a table.