Low Pin Count
The Low Pin Count (LPC) bus is a computer bus used on IBM-compatible personal computers to connect low-bandwidth devices to the CPU, such as the BIOS ROM (BIOS ROM was moved to the Serial Peripheral Interface (SPI) bus in 2006[1]), "legacy" I/O devices (integrated into Super I/O, Embedded Controller, CPLD, and/or IPMI chip), and Trusted Platform Module (TPM).
[2] "Legacy" I/O devices usually include serial and parallel ports, PS/2 keyboard, PS/2 mouse, and floppy disk controller.
Also, LPC is intended to be a motherboard-only bus; there is no standardized connector in common use, though Intel defines one for use for debug modules.
[3] A small number of LPC peripheral daughterboards are available, with pinouts proprietary to the motherboard vendor: Trusted Platform Modules (TPMs),[2] POST cards for displaying BIOS diagnostic codes,[4] and ISA-compatible serial port peripherals for industrial use.
In particular, it shares the restriction that two idle cycles are required to "turn around" any bus signal so that a different device is "speaking".
The exact data transfer rates depend on the type of bus access (I/O, memory, DMA, firmware) performed and by the speed of the host and the LPC device.
The code sent on the last cycle before LFRAME# transitions high defines the following bus transaction.
Normally, the host only holds LFRAME# low for a single clock cycle, for efficiency.
The host pulls LFRAME# low for a minimum of four clock cycles, during which any devices must cease to drive the LAD bus.
In almost all other cases, LPC transactions use the following general structure: DMA transfers differ somewhat.
Three of them end the SYNC phase, while the other three cause the host to wait for another SYNC nibble: Intel designed the LPC bus so that the system BIOS image could be stored in a single flash memory chip directly connected to the LPC bus.
Intel also made it possible to put operating system images and software applications on a single flash memory chip directly connected to the LPC bus, as an alternative to a Parallel ATA port.
[7] During the first cycle with LFRAME# high again, the host drives a "cycle type/direction" (CTDIR) field: two bits indicating the type (I/O, memory, or DMA) and one bit indicating the direction (read from device, or write to device) of the transfer to follow.
This is followed by the transfer address field, whose size depends on the type of cycle: Memory and I/O accesses are allowed as single-byte accesses only, and operate as described in § Transaction structure:: address, data from host if write, turnaround, SYNC, data from device if read.
The "address" consists of 6 bits sent as two nibbles: a 3-bit channel number and 1-bit terminal count indication (the ISA bus's TC pin, or the 8237's EOP# output), followed by a 2-bit transfer size.
As a simplified example: The devices can recognize the beginning of the frame because only the host will ever drive the line low for more than one cycle.
There is also a "quiet" mode in which a device requests a new packet by driving SERIRQ low for one clock cycle.
If it consists of three clocks of low signal, continuous mode follows and only the host may begin a new packet.
If the stop signal consists of two low clocks, quiet mode follows and any device may initiate an interrupt packet.
[7] The supported transfers are: This allows the firmware (BIOS) to be located outside the usual peripheral address space.
[13] These cycles use a START field with the formerly-reserved value of 0101, followed by a CTDIR nibble and 16-bit I/O address just like an ISA-compatible write.
This was done in order to remove ISA's limit on what type of bus master cycles a device is allowed to initiate on which DMA channel.
