The MERSI protocol is a cache coherency and memory coherence protocol used by the PowerPC G4.
[1] The protocol consists of five states, Modified (M), Exclusive (E), Read Only or Recent (R), Shared (S) and Invalid (I).
The R state is similar to the E state in that it is constrained to be the only clean, valid, copy of that data in the computer system.
Unlike the E state, the processor is required to initially request ownership of the cache line in the R state before the processor may modify the cache line and transition to the M state.
In both the MESI and MERSI protocols, the transition from the E to M is silent.