MESI protocol

The Illinois Protocol requires a cache-to-cache transfer on a miss if the block resides in another cache.

The MESI protocol is defined by a finite-state machine that transitions from one state to another based on 2 stimuli.

Every cache has a copy of the sharing status of every block of physical memory it has stored.

The bus has snoopers on both sides: Explanation: Each Cache block has its own 4 state finite-state machine (refer image 1.1).

This can be done by forcing the read to back off (i.e. retry later), then writing the data to main memory and changing the cache line to the Shared state.

The Modified and Exclusive states are always precise: i.e. they match the true cache line ownership situation in the system.

Bus Request Note: The term snooping referred to below is a protocol for maintaining cache coherency in symmetric multiprocessing environments.

The operation is issued by a processor trying to write into a cache line that is in the shared (S) or invalid (I) states of the MESI protocol.

To mitigate these delays, CPUs implement store buffers and invalidate queues.

Note that, unlike the store buffer, the CPU can't scan the invalidation queue, as that CPU and the invalidation queue are physically located on opposite sides of the cache.

Furthermore, memory management units do not scan the store buffer, causing similar problems.

Thus, MESI protocol overcomes this limitation by adding an Exclusive state, which results in saving a bus request.

MSI performs much worse in this case due to the extra bus messages.

Even in the case of a highly parallel application with minimal sharing of data, MESI is far faster.

In case continuous read and write operations are performed by various caches on a particular block, the data has to be flushed to the bus every time.

[7] In case of S (Shared State), multiple snoopers may response with FlushOpt with the same data (see the example above).