MOS Technology 8568

The 8568 was essentially an updated version of the 8563, combining its functionality with glue logic that had previously been implemented using discrete components located near the 8563.

Unlike the 8563, the 8568 included an unused (in the C-128) active low interrupt request line (/INTR), which was asserted when the "ready" bit in the 8568's status register changed from 0 to 1.

Next, the program must wait until the VDC is ready for the access, after which a read or write on the selected internal register may be performed.

The following code is typical of a register read: The following code is typical of a register write operation: Owing to this somewhat cumbersome method of controlling the 8568, the maximum possible frame rate in bit-mapped mode is generally too slow for arcade-style action video games, in which bit-intensive manipulation of the display is required.

The final versions of the 8568 had the revision codes R9a or R9b appended to the part number, apparently indicating undocumented improvements.