Microsecond Bus

The MSB has been developed in the first place for motor management applications in order to reduce the classical pulse-width modulation (PWM) of power loads by a fast serial interface with low pin count and low latency for the downstream to the smart power device.

The downstream from master to slave is synchronous with low latency, while the upstream, mainly used to send diagnostic information from the slave back to the master is asynchronous, and can be slower.

The name of the bus originates from the time of one microsecond to transmit 16 bits in one of the first implementations.

The bus was developed by Infineon and published in SAE International in 2005.

The MSC downlink specifies: In case of LVDS signaling FDA and FCL are split into four differential lines.

MSC signalling scheme: fast downstream (TTL = red, TTL or LVDS = yellow), slow upstream (TLL = green)
Example timing diagram of a MSB frame in LVDS mode (single-ended slave select, LVDS clock and data).