Overlay control has always played an important role in semiconductor manufacturing, helping to monitor layer-to-layer alignment on multi-layer device structures.
Misalignment of any kind can cause short circuits and connection failures, which in turn impact fab yield and profit margins.
Overlay control has become even more critical now because the combination of increasing pattern density and innovative techniques such as double patterning and 193 nm immersion lithography creates a novel set of pattern-based yield challenges at the 45 nm technology node and below.
This combination causes error budgets to shrink below 30 percent of design rules, where existing overlay metrology solutions cannot meet total measurement uncertainty (TMU) requirements.
Higher order overlay control and in-field metrology using smaller, micro-grating or other novel targets are becoming essential for successful production ramps and higher yields at 45 nm and beyond.