Parallel ATA (PATA), originally AT Attachment, also known as Integrated Drive Electronics (IDE), is a standard interface designed for IBM PC-compatible computers.

As a result, many near-synonyms for ATA/ATAPI and its previous incarnations are still in common informal use, in particular Extended IDE (EIDE) and Ultra ATA (UATA).

Called the "primary" and "secondary" ATA interfaces, they were assigned to base addresses 0x1F0 and 0x170 on ISA bus systems.

The first version of what is now called the ATA/ATAPI interface was developed by Western Digital under the name Integrated Drive Electronics (IDE).

The integrated controller presented the drive to the host computer as an array of 512-byte blocks with a relatively simple command interface.

[18][19] A short-lived, seldom-used implementation of ATA was created for the IBM XT and similar machines that used the 8-bit version of the ISA bus.

[20] In 1994, about the same time that the ATA-1 standard was adopted, Western Digital introduced drives under a newer name, Enhanced IDE (EIDE).

Ultra ATA, abbreviated UATA, is a designation that has been primarily used by Western Digital for different speed enhancements to the ATA/ATAPI standards.

The first of these BIOS limits occurred when ATA drives reached sizes in excess of 504 MiB, because some motherboard BIOSes would not allow C/H/S values above 1024 cylinders, 16 heads, and 63 sectors.

It was eventually determined that these size limitations could be overridden with a small program loaded at startup from a hard drive's boot sector.

However, if the computer was booted in some other manner without loading the special utility, the invalid BIOS settings would be used and the drive could either be inaccessible or appear to the operating system to be damaged.

Some PCs and laptops of the era have a SATA hard disk and an optical drive connected to PATA.

Motherboard vendors still wishing to offer Parallel ATA with those chipsets must include an additional interface chip.

Even with earlier adapters without independent timing, this effect applies only to the data transfer phase of a read or write operation.

In other words, the manual master/slave setting using jumpers on the drives takes precedence and allows them to be freely placed on either connector of the ribbon cable.

The function of serializing requests to the interface is usually performed by a device driver in the host operating system.

However, support for these is extremely rare in actual parallel ATA products and device drivers because these feature sets were implemented in such a way as to maintain software compatibility with its heritage as originally an extension of the ISA bus.

By contrast, overlapped and queued operations have been common in other storage buses; in particular, SCSI's version of tagged command queuing had no need to be compatible with APIs designed for ISA, allowing it to attain high performance with low overhead on buses which supported first party DMA like PCI.

The Serial ATA standard has supported native command queueing (NCQ) since its first release, but it is an optional feature for both host adapters and target devices.

[37] While the ATA lock is intended to be impossible to defeat without a valid password, there are purported workarounds to unlock a device.

[citation needed] For NVMe drives, the security features, including lock passwords, were defined in the OPAL standard.

The following table shows the names of the versions of the ATA standards and the transfer modes and rates supported by each.

Congestion on the host bus to which the ATA adapter is attached may also limit the maximum burst transfer rate.

In addition, no ATA hard drives existed in 2005 that were capable of measured sustained transfer rates of above 80 MB/s.

Furthermore, sustained transfer rate tests do not give realistic throughput expectations for most workloads: They use I/O loads specifically designed to encounter almost no delays from seek time or rotational latency.

Hard drive performance under most workloads is limited first and second by those two factors; the transfer rate on the bus is a distant third in importance.

Therefore, transfer speed limits above 66 MB/s really affect performance only when the hard drive can satisfy all I/O requests by reading from its internal cache—a very unusual situation, especially considering that such data is usually already buffered by the operating system.

[43] Only the Ultra DMA modes use CRC to detect errors in data transfer between the controller and drive.

An ARMD-compliant BIOS allows these devices to be booted from and used under the operating system without requiring device-specific code in the OS.

No interfacing chips or circuitry are required, other than to directly adapt the smaller CF socket onto the larger ATA connector.