An inferior placement assignment will not only affect the chip's performance but might also make it non-manufacturable by producing excessive wire-length, which is beyond available routing resources.
A placer takes a given synthesized circuit netlist together with a technology library and produces a valid placement layout.
The layout is optimized according to the aforementioned objectives and ready for cell resizing and buffering — a step essential for timing and signal integrity satisfaction.
In the case of application-specific integrated circuits, or ASICs, the chip's core layout area comprises a number of fixed height rows, with either some or no space between them.
On the other hand, blocks are typically larger than cells and have variable heights that can stretch a multiple number of rows.
[2] Placement maps the circuit's subcircuits into programmable FPGA logic blocks in a manner that guarantees the completion of the subsequent stage of routing.
Total wirelength is typically the primary objective of most existing placers and serves as a precursor to other optimizations because, e.g., power and delay tend to grow with wire length.
When IC designs grew to millions of components, placement leveraged hypergraph partitioning[5] using nested-partitioning frameworks such as Capo.
[6] Combinatorial methods directly prevent component overlaps but struggle with interconnect optimization at large scale.
[9] The majority of modern quadratic placers (KraftWerk,[10] FastPlace,[11] SimPL[12]) follow this framework, each with different heuristics on how to determine the linear density force.
In 2021, Google Brain reported good results from the use of AI techniques (in particular reinforcement learning) for the placement problem.
[17] However, this result is quite controversial,[18][19][20] as the paper does not contain head-to-head comparisons to existing placers, and is difficult to replicate due to proprietary content.