Power network design (IC)

High average current densities lead to undesirable wearing out of metal wires due to electromigration (EM).

These issues are prominent in high performance chips such as microprocessors, since large amounts of power have to be distributed through a hierarchy of many metal layers.

A robust power distribution network is vital in meeting performance guarantees and ensuring reliable operation.

Capacitance between power and ground distribution networks, referred to as decoupling capacitors or decaps, acts as local charge storage and is helpful in mitigating the voltage drop at supply points.

These explicitly added decoupling capacitances are not free and increase the area and leakage power consumption of the chip.

Parasitic interconnect resistance, decoupling capacitance and package/interconnect inductance form a complex RLC circuit which has its own resonance frequency.

Nevertheless, decisions about the structure, size and layout of the power grid have to be made at very early stages when a large part of the chip design has not even begun.

Clock gating, which is a preferred scheme for power management of high performance designs, can cause rapid surges in current demands of macro-blocks and increase di/dt effects.

Designers rely on the on-chip parasitic capacitances and intentionally added decoupling capacitors to counteract the di/dt variations in the voltage.

A critical issue in the analysis of power grids is the large size of the network (typically millions of nodes in a state-of-the-art microprocessor).

Next, these devices are modeled as independent time-varying current sources for simulating the power grid and the voltage drops at the transistors are measured.