Priority encoder

A priority encoder is a circuit or algorithm that compresses multiple binary inputs into a smaller number of outputs, similar to a simple encoder.

The output of a priority encoder is the binary representation of the index of the most significant activated line.

In contrast to the simple encoder, if two or more inputs to the priority encoder are active at the same time, the input having the highest priority will take precedence.

It is an improvement on a simple encoder because it can handle all possible input combinations, but at the cost of extra logic.

[1] Applications of priority encoders include their use in interrupt controllers (to allow some interrupt requests to have higher priority than others), decimal or binary encoding, and analog-to-digital / digital to-analog conversion.

[2] A truth table of a single bit 4-to-2 priority encoder is shown, where the inputs are shown in decreasing order of priority left-to-right, and "x" indicates a don't care term - i.e. any input value there yields the same output since it is superseded by a higher-priority input.

The (usually-included[a]) "v" output indicates if the input is valid.

The location of this fragment is the higher part of the overall index, and steers the exact location within the fragment itself to produce the lower part of the overall index.

If Altera's Stratix V or equivalent device is used,

is recommended to achieve higher performance and area compression, since the mux can be implemented using 6-LUT, hence an entire ALM.

An open-source Verilog generator for the recursive priority-encoder is available online.

A behavioral description of priority encoder in Verilog is as follows.

[6]A simple encoder circuit is a one-hot to binary converter.