Reconvergent fan-out is a technique to make VLSI logic simulation less pessimistic.
These uncertain delays add up so, after passing through many devices, the worst-case timing for a signal could be unreasonably pessimistic.
When this happens, you can remove a fair amount of uncertainty from the total delay because you know that they shared a common path for a while.
This tightens up the worst-case estimation for the signal delay, and usually allows a small but important speedup of the overall device.
The term reconvergent fan-out has been used to describe similar optimizations in graph theory and static code analysis.