[3] Simulations have the advantage of providing a familiar look and feel to the user in that it is constructed from the same language and symbols used in design.
As the design matures, the simulation will require more time and resources to run, and errors will take progressively longer to be found.
[6] Event simulation allows the design to contain simple timing information – the delay needed for a signal to travel from one place to another.
Optimized implementations may take advantage of low model activity to speed up simulation by skipping evaluation of gates whose inputs didn't change.
However, chip design trends point to event simulation gaining relative performance due to activity factor reduction in the circuit (due to techniques such as clock gating and power gating, which are becoming much more commonly used in an effort to reduce power dissipation).