While such timing measurements can theoretically be performed using a rigorous circuit simulation, such an approach is liable to be too slow to be practical.
One of the earliest descriptions of a static timing approach was based on the Program Evaluation and Review Technique (PERT), in 1966.
[3][4][5] In a synchronous digital system, data is supposed to move in "lockstep", advancing one stage on each tick of the clock signal.
The main goal of static timing analysis is to verify that despite these possible variations, all signals will arrive neither too early nor too late, and hence proper circuit operation can be assured.
Behavior of an electronic circuit is often dependent on various factors in its environment like temperature or local voltage variations.
Statistical STA, which replaces delays with distributions, and tracking with correlation, offers a more sophisticated approach to the same problem.
Statistical static timing analysis (SSTA)[7] is a procedure that is becoming increasingly necessary to handle the complexities of process and environmental variations in integrated circuits.