STEbus
It was popular for industrial control systems in the late 1980s and early 1990s before the ubiquitous IBM PC dominated this market.
[2] Although no longer competitive in its original market, it is valid choice for hobbyists wishing to make 'home brew' computer systems.
The VMEbus had provided a high-quality solution for high-performance 16-bit processors, using reliable DIN 41612 connectors and well-specified Eurocard board sizes and rack systems.
In the mid 1980s, the STEbus standard addressed these issues by specifying what is rather like a VMEbus simplified for 8-bit processors.
These boards included the Intel 8031, 8085, 8088, 80188; the National Semiconductor 32008 and 32016; the Motorola 6809, 68000, and 68008; The Zilog Z80 and Z280; the Hitachi HD64180; and the Inmos Transputer.
can use the STEbus if the processor can handle data in byte-wide chunks, giving the slave as long as it needs to respond.
The only popular micro notably absent was the 6502, because it did not naturally support wait-states while writing.
The STEbus achieved its goal of providing a rack-mounting system robust enough for industrial use, with easily interchangeable boards and processor independence.
[6] The STEbus market began to decline as the IBM PC made progress into industrial control systems.
Customers opted for PC-based products as the software base was larger and cheaper.
As time went on, PC systems did away with the need for card cages and backplanes by moving to the PC/104 format where boards stack onto each other.
[citation needed] The major manufacturers from its peak period now support STEbus mostly for goodwill with old customers who bought a lot of product from them.
[citation needed][editorializing] As of 2013, some manufacturers still support STEbus, G64, Multibus II, and other legacy bussed systems.
CM2 low state is used only during "attention request" phases (for interrupts and/or DMA cycles) for Explicit Response mode.
When Implicit Response mode is used, the bus master polls the slave boards to find which one has triggered the Attention Request and reset the signal source.
These are reserved for boards to signal for processor attention, a term which covers Interrupts and Direct Memory Access (DMA).
The number of Attention Requests reflects the intended role of the STEbus, in real-time control systems.
A slave will assert this signal when to acknowledge the safe completion of a data transfer via the STEbus.
A slave will assert this signal when acknowledging the erroneous completion of a data transfer via the STEbus.
The STEbus spec was later firmed up to say that slaves were not allowed to start transfers until DATSTB* was ready, so ADRSTB* has become quite redundant.
Nowadays, STEbus masters can simply generate DATSTB* and ADRSTB* from the same logic signal.
So a STEbus expansion card sees the same signals no matter which slot of the backplane it is plugged into.
The System Controller is also in charge of the Bus Arbitration in case there are multiple masters.
