Scientific Research Institute of System Analysis (abbrev.
The mission of the institute is to resolve complex applied problems on the basis of fundamental and applied mathematics in combination with the methods of practical computing.
Main lines of activities: The SRISA has designed several MIPS compatible CPUs for general purpose calculations.
These include: Dual-core 64-bit superscalar microprocessor with KOMDIV64 architecture with integrated system and peripheral controllers, second-level cache memory and additional functions for digital signal processing.
Main characteristics: ·support for 32-bit instruction execution mode and addressing mode; ·the presence of a real arithmetic coprocessor that supports the formats for representing real numbers of single (32 bits) and double (64 bits) precision, as well as the format "pair of real numbers of single precision"; ·the presence of a specialized vector coprocessor optimized for linear algebra and digital signal processing tasks of single and double precision with a separate register file of 64 128-bit registers, supporting single and double precision real and complex number formats; ·translation of 32-bit and 64-bit virtual addresses into 36-bit physical ones; ·64-address (128-page) virtual translation lookaside buffer (jTLB); ·separate virtual address translation buffer (micro TLB) caches for 4 addresses for instructions and data, transparent to the software model; ·separate set-associative first-level instruction caches of 32 KB (8 sections) and data of 16 KB (4 sections); ·2-level cache memory of 512 KB (4 sections); ·128-bit internal bus; ·7-stage superscalar pipeline with instruction prefetching and the ability to execute two instructions per cycle; ·reading up to four commands per clock cycle; ·dynamic branch prediction and speculative instruction execution.