Asynchronous circuit

However asynchronous circuits have a potential to be much faster, have a lower level of power consumption, electromagnetic interference, and better modularity in large systems.

In synchronous logic circuits, an electronic oscillator generates a repetitive series of equally spaced pulses called the clock signal.

Flip-flops only flip when triggered by the edge of the clock pulse, so changes to the logic signals throughout the circuit begin at the same time and at regular intervals.

The changes in signal require a certain amount of time to propagate through the combinational logic gates of the circuit.

As of 2021[update], timing of modern synchronous ICs takes significant engineering efforts and sophisticated design automation tools.

A widely distributed clock network dissipates a lot of useful power and must run whether the circuit is receiving inputs or not.

[6] Because of this level of complexity, testing and debugging takes over half of development time in all dimensions for synchronous circuits.

[7]: xiv [3]: 4 Since asynchronous circuits do not have to wait for a clock pulse to begin processing inputs, they can operate faster.

This is because the resulting state of an asynchronous circuit can be sensitive to the relative arrival times of inputs at gates.

If transitions on two inputs arrive at almost the same time, the circuit can go into the wrong state depending on slight differences in the propagation delays of the gates.

[9] The term "asynchronous logic" is used to describe a variety of design styles, which use different assumptions about circuit properties.

The latter style tends to yield circuits which are larger than bundled data implementations, but which are insensitive to layout and parametric variations and are thus "correct by design".

These function without a clock signal and so individual logic elements cannot be relied upon to have a discrete true/false state at any given time.

[16][17] Scott C. Smith and Jia Di developed an ultra-low-power variation of Fant's Null Convention Logic that incorporates multi-threshold CMOS.

A particularly useful type of interpreted Petri nets, called Signal Transition Graphs (STGs), was proposed independently in 1985 by Leonid Rosenblum and Alex Yakovlev[20] and Tam-Anh Chu.

[21] Since then, STGs have been studied extensively in theory and practice,[22][23] which has led to the development of popular software tools for analysis and synthesis of asynchronous control circuits, such as Petrify[24] and Workcraft.

Both quasi-delay-insensitive (QDI) circuits (generally agreed to be the most "pure" form of asynchronous logic that retains computational universality)[citation needed] and less pure forms of asynchronous circuitry which use timing constraints for higher performance and lower area and power present several advantages.

Many other, less common protocols have been proposed including using a single wire for request and acknowledgment, using several significant voltages, using only pulses or balancing timings in order to remove the latches.

Instead, stages of the CPU are coordinated using logic devices called "pipeline controls" or "FIFO sequencers".

[37][38] The ILLIAC II was the first completely asynchronous, speed independent processor design ever built; it was the most powerful computer at the time.

Since the mid-1980s, Caltech has designed four non-commercial CPUs in attempt to evaluate performance and energy efficiency of the asynchronous circuits.

[39]: 12 During demonstrations, the researchers loaded a simple program which ran in a tight loop, pulsing one of the output lines after each instruction.

[39]: 5  Overall, the research paper interpreted the resultant performance of CAM as superior compared to commercial alternatives available at the time.

The processor is intended for use in smart cards, whose chips are currently limited in size to those small enough that they can remain perfectly rigid.

IBM's chip consumes orders of magnitude less power than traditional computing systems on pattern recognition benchmarks.

Illustration of two and four-phase handshakes. Top: A sender and a receiver are communicating with simple request and acknowledge signals. The sender drives the request line, and the receiver drives the acknowledge line. Middle: Timing diagram of two, two-phase communications. Bottom: Timing diagram of one, four-phase communication.
A 4-phase, bundled-data communication. Top: A sender and receiver are connected by data lines, a request line, and an acknowledge line. Bottom: Timing diagram of a bundled data communication. When the request line is low, the data is to be considered invalid and liable to change at any time.
Diagram of dual rail and 1-of-4 communications. Top: A sender and receiver are connected by data lines and an acknowledge line. Middle: Timing diagram of the sender communicating the values 0, 1, 2, and then 3 to the receiver with the 1-of-4 encoding. Bottom: Timing diagram of the sender communicating the same values to the receiver with the dual-rail encoding. For this particular data size, the dual rail encoding is the same as a 2x1-of-2 encoding.