Serial Peripheral Interface
Motorola's original specification (from the early 1980s) uses four logic signals, aka lines or wires, to support full duplex communication.
Each device internally uses a shift register for serial communication, which together forms an inter-chip circular buffer.
To begin communication, the SPI main first selects a sub device by pulling its CS low.
(Note: the bar above CS indicates it is an active low signal, so a low voltage means "selected", while a high voltage means "not selected") If a waiting period is required, such as for an analog-to-digital conversion, the main must wait for at least that period of time before issuing clock cycles.
It is common for different devices to use SPI communications with different lengths, as, for example, when SPI is used to access an IC's scan chain by issuing a command word of one size (perhaps 32 bits) and then getting a response of a different size (perhaps 153 bits, one for each pin in that scan chain).
Microcontrollers configured as sub devices may have hardware support for generating interrupt signals to themselves when data words are received or overflow occurs in a receive FIFO buffer,[6] and may also set up an interrupt routine when their chip select input line is pulled low or high.
Examples include pen-down interrupts from touchscreen sensors, thermal limit alerts from temperature sensors, alarms issued by real-time clock chips, SDIO[note 7] and audio jack insertions for an audio codec.
Software for attached devices is written to call a "bus driver" that handles the actual low-level SPI hardware.
This permits the driver code for attached devices to port easily to other hardware or a bit-banging software implementation.
The pseudocode below outlines a software implementation ("bit-banging") of SPI's protocol as a main with simultaneous output and input.
One solution is to configure all GPIOs used for CS to output a high voltage for all subs before running initialization code from any of those software libraries.
[7] In addition to using SPI-specific subs, daisy-chained SPI can include discrete shift registers for more pins of inputs (e.g. using the parallel-in serial-out 74xx165)[8] or outputs (e.g. using the serial-in parallel-out 74xx595)[9] chained indefinitely.
Expander configurations use SPI-controlled addressing units (e.g. binary decoders, demultiplexers, or shift registers) to add chip selects.
These chips usually include SPI controllers capable of running in either main or sub mode.
[12] Chip or FPGA based designs sometimes use SPI to communicate between internal components; on-chip real estate can be as costly as its on-board cousin.
And for high-performance systems, FPGAs sometimes use SPI to interface as a sub to a host, as a main to sensors, or for flash memory used to bootstrap if they are SRAM-based.
Some variations are minor or informal, while others have an official defining document and may be considered to be separate but related protocols.
[14] Motorola's 1987 Application Node AN991 "Using the Serial Peripheral Interface to Communicate Between Multiple Microcomputers"[15] (now under NXP, last revised 2002[5]) informally serves as the "official" defining document for SPI.
Some devices require an additional flow control signal from sub to main, indicating when data is ready.
Examples include initiating an ADC conversion, addressing the right page of flash memory, and processing enough of a command that device firmware can load the first word of the response.
Three-wire tends to be used for lower-performance parts, such as small EEPROMs used only during system startup, certain sensors, and Microwire.
For instances where the full-duplex nature of SPI is not used, an extension uses both data pins in a half-duplex configuration to send two bits per clock cycle.
JTAG is specifically intended to provide reliable test access to the I/O pins from an off-board controller with less precise signal delay and skew parameters, while SPI has many varied applications.
[29] SGPIO is essentially another (incompatible) application stack for SPI designed for particular backplane management activities.
Intel aims to reduce the number of pins required on motherboards and increase throughput compared to LPC, reduce the working voltage to 1.8 volts to facilitate smaller chip manufacturing processes, allow eSPI peripherals to share SPI flash devices with the host (the LPC bus did not allow firmware hubs to be used by LPC peripherals), tunnel previous out-of-band pins through eSPI, and allow system designers to trade off cost and performance.
[30] Communications that were out-of-band of LPC like general-purpose input/output (GPIO) and System Management Bus (SMBus) should be tunneled through eSPI via virtual wire cycles and out-of-band message cycles respectively in order to remove those pins from motherboard designs using eSPI.
For instance, the Raspberry Pi's J8 header exposes at least two SPI units that can be used via Linux drivers or python.
They are used for embedded systems, chips (FPGA, ASIC, and SoC) and peripheral testing, programming and debugging.
It is possible to find SPI adapters on the market today that support up to 100 MHz serial interfaces, with virtually unlimited access length.
Most logic analyzers have the capability to decode SPI bus signals into high-level protocol data with human-readable labels.
