Single-electron transistor

A single-electron transistor (SET) is a sensitive electronic device based on the Coulomb blockade effect.

In this device the electrons flow through a tunnel junction between source/drain to a quantum dot (conductive island).

The conductive island is sandwiched between two tunnel junctions[1] modeled by capacitors,

A new subfield of condensed matter physics began in 1977 when David Thouless pointed out that, when made small enough, the size of a conductor affects its electronic properties.

[2] This was followed by mesoscopic physics research in the 1980s based on the submicron-size of systems investigated.

The first single-electron transistor based on the phenomenon of Coulomb blockade was reported in 1986 by Soviet scientists K. K. Likharev [ru] and D. V.

[4] A couple years later, T. Fulton and G. Dolan at Bell Labs in the US fabricated and demonstrated how such a device works.

[5] In 1992 Marc A. Kastner demonstrated the importance of the energy levels of the quantum dot.

[6] In the late 1990s and early 2000s, Russian physicists S. P. Gubin, V. V. Kolesov, E. S. Soldatov, A. S. Trifonov, V. V. Khanin, G. B. Khomutov, and S. A. Yakovenko were the first ones to demonstrate a molecule-based SET operational at room temperature.

For this purpose, ultra-low power consumption is one of the main research topics into the current electronics world.

The amazing number of tiny computers used in the day-to-day world (e.g. mobile phones and home electronics) requires a significant power consumption level of the implemented devices.

In this scenario, the SET has appeared as a suitable candidate to achieve this low power range with high level of device integration.

The source and drain are coupled through two tunnel junctions, separated by a metallic or semiconductor-based quantum nanodot (QD),[9] also known as the "island".

), after which it scatters inelastically and reaches the drain electrode Fermi level (4.).

it is enough to confine the electrons to the island, and it is safe to ignore coherent quantum processes consisting of several simultaneous tunnelling events, i.e. co-tunnelling.

) we have the condition (that is, the threshold voltage is reduced by half compared with a single transition).

When the applied voltage is zero, the Fermi level at the metal electrodes will be inside the energy gap.

When the voltage increases to the threshold value, tunnelling from left to right occurs, and when the reversed voltage increases above the threshold level, tunnelling from right to left occurs.

The existence of the Coulomb blockade is clearly visible in the current–voltage characteristic of a SET (a graph showing how the drain current depends on the gate voltage).

At low gate voltages (in absolute value), the drain current will be zero, and when the voltage increases above the threshold, the transitions behave like an ohmic resistance (both transitions have the same permeability) and the current increases linearly.

The background charge in a dielectric can not only reduce, but completely block the Coulomb blockade.

The gate electrode can change the background charge in the dielectric, since the gate additionally polarizes the island so that the island charge becomes equal to Substituting this value into the formulas found above, we find new values for the voltages at the transitions: The electrostatic energy should include the energy stored on the gate capacitor, and the work performed by the voltage on the gate should be taken into account in the free energy: At zero temperatures, only transitions with negative free energy are allowed:

As mentioned in bullet 2 in the list above: the electrostatic charging energy must be greater than

This in turn puts huge restraints on the manufacturability of integrated circuits because of reproducibility issues.

The level of the electrical current of the SET can be amplified enough to work with available CMOS technology by generating a hybrid SET–FET device.

[12][13] The EU funded, in 2016, project IONS4SET (#688072)[14] looks for the manufacturability of SET–FET circuits operative at room temperature.

The main goal of this project is to design a SET-manufacturability process-flow for large-scale operations seeking to extend the use of the hybrid SET–CMOS architectures.

To assure room temperature operation, single dots of diameters below 5 nm have to be fabricated and located between source and drain with tunnel distances of a few nanometers.

[15] Up to now there is no reliable process-flow to manufacture a hybrid SET–FET circuit operative at room temperature.

In this context, this EU project explores a more feasible way to manufacture the SET–FET circuit by using pillar dimensions of approximately 10 nm.