However the increased variation in semiconductor devices and interconnect has introduced a number of issues that cannot be handled by traditional (deterministic) STA.
This has led to considerable research into statistical static timing analysis, which replaces the normal deterministic timing of gates and interconnects with probability distributions, and gives a distribution of possible circuit outcomes rather than a single outcome.
Historically, this seemed like a big burden to add to STA, whereas it was clear it was needed for SSTA, so no-one complained.
A path-based algorithm[1] sums gate and wire delays on specific paths.
The statistical calculation is simple, but the paths of interest must be identified prior to running the analysis.