Altos developed and marketed cell and semiconductor intellectual property (IP) characterization tools that created library views for timing, signal integrity and power analysis and optimization.

The Altos tools were used by engineers employing both corner-based and statistical-based design implementation flows to reduce time-to -market and improve yield.

All members of the team worked at CadMOS where they were responsible for the development of Signal Integrity analysis tools for both cell- and transistor-level digital IC designers.

[5] Variety creates statistical timing cell models that represent the non-linear impact of any number of systematic and random parameter variations.

Liberate is an automated library characterization tool for standard cells and I/Os that serves existing static timing analyzers.