SystemVerilog started with the donation of the Superlog language to Accellera in 2002 by the startup company Co-Design Automation.
SystemVerilog extends the reg type so it can be driven by a single driver such as gate or module.
SystemVerilog names this type "logic" to remind users that it has this extra capability and is not a hardware register.
A signal with more than one driver (such as a tri-state buffer for general-purpose input/output) needs to be declared a net type such as "wire" so SystemVerilog can resolve the final value.
The built-in function name() returns an ASCII string for the current enumerated value, which is useful in validation and testing.
The contents of struct data types occupy a continuous block of memory with no gaps, similar to bitfields in C and C++: As shown in this example, SystemVerilog also supports typedefs, as in C and C++.
An HDL compiler or verification program can take extra steps to ensure that only the intended type of behavior occurs.
The simulator infers the sensitivity list to be all variables from the contained statements: An always_latch block models level-sensitive latches.
Again, the sensitivity list is inferred from the code: An always_ff block models synchronous logic (especially edge-sensitive sequential logic): Electronic design automation (EDA) tools can verify the design's intent by checking that the hardware model does not violate any block usage semantics.
SystemVerilog introduces concept of interfaces to both reduce the redundancy of port-name declarations between connected modules, as well as group and abstract related signals into a user-declared bundle.
Example: The following verification features are typically not synthesizable, meaning they cannot be implemented in hardware based on HDL code.
Finally, a queue provides much of the functionality of the C++ STL deque type: elements can be added and removed from either end efficiently.
These primitives allow the creation of complex data structures required for scoreboarding a large design.
SystemVerilog has automatic garbage collection, so there is no language facility to explicitly destroy instances created by the new operator.
Example: Integer quantities, defined either in a class definition or as stand-alone variables in some lexical scope, can be assigned random values based on a set of constraints.
The below code describes and procedurally tests an Ethernet frame: Assertions are useful for verifying properties of a design that manifest themselves after a specific condition or state is reached.
Property coverage allows the verification engineer to verify that assertions are accurately monitoring the design.
[vague] Coverage as applied to hardware verification languages refers to the collection of statistics based on sampling events within the simulation.
Functional coverage ensures that all desired corner and edge cases in the design space have been explored.
A SystemVerilog coverage group creates a database of "bins" that store a histogram of values of an associated variable.
Verilog's 'event' primitive allowed different blocks of procedural statements to trigger each other, but enforcing thread synchronization was up to the programmer's (clever) usage.
Typically, objects are class instances representing transactions: elementary operations (for example, sending a frame) that are executed by the verification components.
The three largest EDA vendors (Cadence Design Systems, Mentor Graphics, Synopsys) have incorporated SystemVerilog into their mixed-language HDL simulators.
Although no simulator can yet claim support for the entire SystemVerilog Language Reference Manual, making testbench interoperability a challenge, efforts to promote cross-vendor compatibility are underway.[when?]
In 2008, Cadence and Mentor released the Open Verification Methodology, an open-source class-library and usage-framework to facilitate the development of re-usable testbenches and canned verification-IP.
In the design synthesis role (transformation of a hardware-design description into a gate-netlist), SystemVerilog adoption has been slow.
Most design teams cannot migrate to SystemVerilog RTL-design until their entire front-end tool suite (linters, formal verification and automated test structure generators) support a common language subset.