TI-990

Among its core concepts was the ability to support multiprogramming using a software-switchable set of processor registers that allowed it to perform rapid context switches between programs.

This was enabled through the use of register values stored in main memory that could be swapped by changing a single pointer.

This chip was widely used in the TI-99/4A home computer, where details of its minicomputer-style memory model presented significant disadvantages.

The concept behind the workspace is that main memory was based on the new semiconductor RAM chips that TI had developed and ran at the same speed as the CPU.

A context switch entailed the saving and restoring of only the hardware registers.

[citation needed] If the hardware is not present the CPU traps to allow software to perform the function.

On the 990/12, the XOP instruction could run microcode from the machine's Writable Control Store.

The model 990/12 CPU allowed for a four word instruction with the extended mode operations.

[clarification needed] The first field of the word specifies the operation to be performed, the second field is a relative offset to where to go, for JMP instructions, or the relative offset for CRU bit addressing.

[clarification needed] The multiple precision instructions allowed for logic and integer arithmetic on operands from 1-15 bytes long.

The following program is a standalone version that prints on the serial terminal connected to CRU address 0.

The TI-990 processors fell into several natural groups depending on the original design upon which they are based and which I/O bus they used.

All models supported the Communications Register Unit (CRU) which is a serial bit addressable I/O bus.

Also, supported on higher end models was the TILINE I/O bus which is similar to DEC's popular UNIBUS.

The TILINE also supported a master/slave relationship that allowed multiple CPU boards in a common chassis with arbitration control.