It is "orthogonal" in the sense that the instruction type and the addressing mode may vary independently.
Modern CPUs often simulate orthogonality in a preprocessing step before performing the actual tasks in a RISC-like core.
[b] While being worked on, data can be temporarily held in processor registers, scratchpad values that can be accessed very quickly.
[3] In early computers, the instruction set architecture (ISA) often used a single register, in which case it was known as the accumulator.
This very simple example ISA has a "one-address format" because each instruction includes the address of the data.
One very common pattern is that a single operation may be applied across a large amount of similar data.
In a simple two-address format of instructions,[d] there is no way to change the address, so 1,000 additions have to be written in the machine language.
This means the programmer can change the address by performing addition on that memory location or register.
The reason for this design is not aesthetic, the goal is to reduce the total size of a program's object code.
This means the total number of instructions is reduced, both saving memory and improving performance.
[5] As a result, the time needed to complete different variations of an instruction can vary widely, which adds complexity to the overall CPU design.
[5] In the late 1970s, with the first high-powered fully orthogonal designs emerging, the goal widened to become the high-level language computer architecture, or HLLCA for short.
[5] Instructions such as 'ADD' were divided into data-size dependent variants such as ADDB, ADDW, ADDL, ADDP, ADDF for add byte, word, longword, packed BCD and single-precision floating point, respectively.
[8] The general form of a VAX-11 instruction would be: Each component being one byte, the opcode a value in the range 0–255, and each operand consisting of two nibbles, the upper 4 bits specifying an addressing mode, and the lower 4 bits (usually) specifying a register number (R0–R15).
Although this had to change due to legal issues, the resulting system retained much of the VAX-11's overall design philosophy and remained completely orthogonal.
The binary-compatible Z80 later added prefix-codes to escape from this 1-byte limit and allow for a more powerful instruction set.
A number of studies through the 1970s demonstrated that the flexibility offered by orthogonal modes was rarely or never used in actual problems.
In particular, an effort at IBM studied traces of code running on the System/370 and demonstrated that only a fraction of the available modes were being used in actual programs.
This meant the time needed to access data from memory was growing in relative terms in comparison to the speed of the CPUs.
Finally, a paper by Andrew Tanenbaum demonstrated that 97% of all the constants in a program are between 0 and 10, with 0 representing between 20 and 30% of the total.
RISC processors generally have only two addressing modes, direct (constant) and register.
All of the other modes found in older processors are handled explicitly using load and store instructions moving data to and from the registers.