It proved very difficult to get good coverage of potential faults, so Design for testability (DFT) based on scan and automatic test pattern generation (ATPG) were developed to explicitly test each gate and path in a design.
In general, the idea is to modify the design to increase the number of internal scan chains, each of shorter length.
Experimental results show that for industrial circuits with test vectors and responses with very low fill rates, ranging from 3% to 0.2%, the test compression based on this method often results in compression ratios of 30 to 500 times.
The compactor must be synchronized with the data decompressor, and must be capable of handling unknown (X) states.
Another design criteria for the test result compressor is that it should give good diagnostic capabilities, not just a yes/no answer.