A fault model is a mathematical description of how a defect alters design behavior.
The classic example of this is a redundant circuit, designed such that no single fault causes the output to change.
It is also called a permanent fault model because the faulty effect is assumed to be permanent, in contrast to intermittent faults which occur (seemingly) at random and transient faults which occur sporadically, perhaps depending on operating conditions (e.g. temperature, power supply voltage) or on the data values (high or low voltage states) on surrounding signal lines.
During test, a so-called scan-mode is enabled forcing all flip-flops (FFs) to be connected in a simplified fashion, effectively bypassing their interconnections as intended during normal operation.
However, according to reported results, no single strategy or heuristic out-performs others for all applications or circuits.
This observation implies that a test generator should include a comprehensive set of heuristics.
Even a simple stuck-at fault requires a sequence of vectors for detection in a sequential circuit.
For designs that are sensitive to area or performance overhead, the solution of using sequential-circuit ATPG and partial scan offers an attractive alternative to the popular full-scan solution, which is based on combinational-circuit ATPG.
As design trends move toward nanometer technology, new manufacture testing problems are emerging.
During design validation, engineers can no longer ignore the effects of crosstalk and power supply noise on reliability and performance.
Current fault modeling and vector-generation techniques are giving way to new models and techniques that consider timing information during test generation, that are scalable to larger designs, and that can capture extreme design conditions.
Testing very-large-scale integrated circuits with a high fault coverage is a difficult task because of complexity.