The threshold voltage, commonly abbreviated as Vth or VGS(th), of a field-effect transistor (FET) is the minimum gate-to-source voltage (VGS) that is needed to create a conducting path between the source and drain terminals.
[1][2] This is somewhat confusing since pinch off applied to insulated-gate field-effect transistor (IGFET) refers to the channel pinching that leads to current saturation behavior under high source–drain bias, even though the current is never off.
Unlike pinch off, the term threshold voltage is unambiguous and refers to the same concept in any field-effect transistor.
In n-channel enhancement-mode devices, a conductive channel does not exist naturally within the transistor.
A positive VGS attracts free-floating electrons within the body towards the gate.
But enough electrons must be attracted near the gate to counter the dopant ions and form a conductive channel.
The conductive channel connects from source to drain at the FET's threshold voltage.
Even more electrons attract towards the gate at higher VGS, which widens the channel.
The application of a negative gate voltage to the p-type "enhancement-mode" MOSFET enhances the channels conductivity turning it “ON”.
In contrast, n-channel depletion-mode devices have a conductive channel naturally existing within the transistor.
Accordingly, the term threshold voltage does not readily apply to turning such devices on, but is used instead to denote the voltage level at which the channel is wide enough to allow electrons to flow easily.
[citation needed] This ease-of-flow threshold also applies to p-channel depletion-mode devices, in which a negative voltage from gate to body/source creates a depletion layer by forcing the positively charged holes away from the gate-insulator/semiconductor interface, leaving exposed a carrier-free region of immobile, negatively charged acceptor ions.
Likewise for a p-channel "depletion-mode" MOS transistor a sufficient positive gate-source voltage will deplete the channel of its free holes, turning it “OFF”.
In wide planar transistors the threshold voltage is essentially independent of the drain–source voltage (VDS) and is therefore a well defined characteristic, however it is less clear in modern nanometer-sized MOSFETs due to drain-induced barrier lowering.
Therefore, datasheets will specify threshold voltage according to a specified measurable amount of current (commonly 250 μA or 1 mA).
If the gate voltage is above the threshold voltage (right figure), the "enhancement-mode" transistor is turned on, due to there being many electrons in the channel at the oxide-silicon interface, creating a low-resistance channel where charge can flow from drain to source.
For voltages significantly above the threshold, this situation is called strong inversion.
[3] For an enhancement-mode nMOS MOSFET, the body effect upon threshold voltage is computed according to the Shichman–Hodges model,[4] which is accurate for older process nodes,[clarification needed] using the following equation: where;
Although this may seem to be an improvement, it is not without cost; because the thinner the oxide thickness, the higher the subthreshold leakage current through the device will be.
Consequently, the design specification for 90-nm gate-oxide thickness was set at 1 nm to control the leakage current.
Before scaling the design features down to 90 nm, a dual-oxide approach for creating the oxide thickness was a common solution to this issue.
With a 90 nm process technology, a triple-oxide approach has been adopted in some cases.
These differences are based purely on the characteristics of oxide thickness on threshold voltage of CMOS technologies.
[8] For a change of 30 °C this results in significant variation from the 500 mV design parameter commonly used for the 90-nm technology node.
In newer process technologies RDF has a larger effect because the total number of dopants is fewer.
[9] Research works are being carried out in order to suppress the dopant fluctuation which leads to the variation of threshold voltage between devices undergoing same manufacturing process.