Toshiba TLCS

The product line includes multiple families of CISC and RISC architectures.

Individual components generally have a part number beginning with "TMP".

It was a 32 mm2 MOS integrated circuit chip with about 2,800 silicon gates, fabricated on a 6 μm process with NMOS logic.

It omits the separate I/O address space of the Z80, but adds more flexibility to operand combinations, some new operations (notably multiply and divide), and several additional addressing modes: Most of the functionality of 8-bit accumulator A has also been implemented for the 16-bit HL register pair, such as the missing SUB and CP instructions, and the AND, XOR, and OR bitwise instructions.

TLCS-90 SoC packages include the 4-bit BX and BY registers, which get concatenated with effective addresses based on the IX or IY register, allowing the processor to address up to one megabyte of memory.

[7]: 182–184  The same scheme of encoding the addressing mode before the instruction's opcode and additional operands is implemented.

In the minimum mode of early models, there are 8 banks of four 16-bit registers, which can be split into 8-bit halves.

Early models had two separate stack pointers for user and system modes.

Current TLCS processors offer some or all of the following features: As demand for these features differs widely depending on the requirements for a specific project (low energy consumption; high number of I/O ports; etc.

Alfred Arnold's The Macroassembler AS [1] is a free assembler supporting the TLCS-47, TLCS-870, TLCS-90, TLCS-900 and TLCS-9000 families.