VAX 8000
The 8000 series was introduced in October 1984 with the 8600, taking over the high-end of the VAX lineup.
It was intended that the 8800 was to have been replaced by the VAX 9000 on the high end, but this project failed.
Instead, the VAX 6000, originally a mid-range model replacing the 8700/8500, was upgraded to provide almost the same level of performance of the 8800 but at half the cost.
These are single-chip implementations based on the NVAX CPU and are the final dedicated VAX machines.
The VAX 8600 has a CPU with an 80 ns cycle time (12.5 MHz) implemented with emitter coupled logic (ECL) macrocell arrays (MCAs).
These are large scale integration devices fabricated by Motorola in their 3 μm MOSAIC bipolar process.
They are packaged in 68-pin leadless chip carriers or pin grid arrays and are mounted onto the printed circuit board in sockets or soldered in place.
This dedicated bus, which has an 80 ns (12.5 MHz) cycle time, contributes to the improved performance the VAX 8600 has over the VAX-11/780, which access memory via the Synchronous Backplane Interconnect (SBI) shared with I/O devices.
The VAX 8600 I/O cabinet contains a PDP-11 computer serving as the console, a Unibus card cage and provisions for mounting disk drives.
They use the KA820 CPU module containing a V-11 microprocessor operating at 5 MHz (200 ns cycle) and support a maximum of 128 MB of ECC memory.
They use the KA825 CPU module containing a V-11 microprocessor operating at 6.25 MHz (160 ns cycle).
The upgrade kit includes replacement numbers affixed to the front of the machine to reflect the new designation.
Models include the: The VAX 8800 family is based on the NMI bus, which connects the CPU, memory controller and I/O adapters.
The VAX 8800 family central processing unit (CPU) operates at 22.22 MHz (45 ns cycle time) and is implemented with discrete emitter-coupled logic (ECL) devices spread over eight modules.
The memory controller is implemented with ECL gate arrays and resides on an NMI bus module.
The 4 MB array module is an eight-layer printed circuit board populated by metal oxide semiconductor (MOS) dynamic random access memory (DRAM) devices and medium-scale integration (MSI) FAST transistor-transistor logic (TTL) devices in roughly equal numbers.
The NBI adapter handles all CPU references and direct memory access (DMA) transactions to and from the I/O devices.
The adapter operates at 5 MHz and asynchronously to the CPU as it generates its own clock signal.
The RTI has two serial line units: one connects to the VAX environmental monitoring module (EMM) and the other is a spare that can be used for data transfer.
The RTI's programmable 24 bit peripheral interface (PPI) is configured as three 8-bit ports for data, address, and control signals between the Nautilus system console interface and the VAX console.
The console sets configuration registers, loads CPU microcode into the writeable controls store, performs processor module diagnostic tests, resets the TOY clock (time-of-year clock), logs certain types of errors, performs other supervisory functions, and is the interface for field service diagnosis and testing.
